1. Field of the Invention
The present invention relates to a wiring substrate and a semiconductor device and a method of manufacturing the same and, more particularly, a wiring substrate on which a semiconductor chip is flip-chip mounted, and a semiconductor device constructed by flip-chip mounting the semiconductor chip on the wiring substrate and a method of manufacturing the same.
2. Description of the Related Art
In the prior art, there is a semiconductor device that is constructed by flip-chip mounting a semiconductor on a wiring substrate. As shown in FIG. 1, in a wiring substrate 100 of a semiconductor device in the prior art, through holes TH are provided on a core substrate 200 to pass through there, and a through hole plating layer 220 is provided on inner surfaces of the through holes TH respectively. A resin 240 is filled in holes of the through holes TH.
Also, a first wiring layer 300 connected to the through hole plating layers 220 is formed on an upper surface side of the core substrate 200. The first wiring layer 300 is connected to a lower wiring layer (not shown), which is formed on the lower surface side of the core substrate 200, via the through hole plating layers 220. Also, a first interlayer insulating layer 400 is formed on the first wiring layer 300, and first via holes VH1 whose depth is set to arrive at the first wiring layer 300 are formed in the first interlayer insulating layer 400.
A second wiring layer 320 connected to the first wiring layer 300 via the first via holes VH1 is formed on the first interlayer insulating layer 400.
Also, similarly a second interlayer insulating layer 420 is formed on the second wiring layer 320, and second via holes VH2 whose depth is set to arrive at the second wiring layer 320 are provided in the second interlayer insulating layer 420. Also, a third wiring layer 340 connected to the second wiring layer 320 via the second via holes VH2 is formed on the second interlayer insulating layer 420. A solder resist 500 in which opening portions 500a are provided on connection portions respectively is formed on the third wiring layer 340.
Also, solder bumps 620 of a semiconductor chip 600 are flip-chip connected to the connection portions of the third wiring layer 340. Also, an underfill resin 700 is filled in a clearance between the semiconductor chip 600 and the wiring substrate 100.
In Patent Literature 1 (Patent Application Publication (KOKAI) 2000-22317), it is set forth that, in a method of manufacturing a printed-wiring board to which an IC chip is flip-chip connected, by removing an oxide film on the surface of the solder resist and an organic residue on the metal surface of the pads exposed from opening portions in the solder resist by means of an oxygen plasma, the printed-wiring board that is excellent in connectivity and reliability can be obtained.
Meanwhile, in the above semiconductor device, a coefficient of thermal expansion is different between the wiring substrate 100 (a resin, a copper wiring, or the like) and the semiconductor chip (silicon chip) 600. Therefore, a thermal stress is generated when a heat is applied to the semiconductor device, and accordingly a warp occurs in the semiconductor device in some cases.
In recent years, as the semiconductor chip 600, the stained silicon technology has been employed for improving the performance, or the interlayer dielectric layer having low dielectric constant has been employed.
Such high-performance semiconductor chip is relatively weak against the stress, and thus deterioration of operating characteristics is easily caused due to the stress. In the prior art, the underfill resin 700 is employed as the buffer material that absorbs a difference in coefficient of thermal expansion between the wiring substrate 100 and the semiconductor chip 600. However, it is becoming difficult to protect sufficiently the high-performance semiconductor chip, and it is probable that reliability of the semiconductor device becomes an issue.